1. Field
This application relates generally to integrated circuits, and more particularly to testing the affects of thermal hot spots on an integrated circuit.
2. Background
When operating an integrated circuit (IC), thermal hot spots occur at different regions of the IC. Increases in temperature impact the available design margin. The affects of temperature on an IC applies to both two-dimensional and three-dimensional devices. For three-dimensional devices, thermal hot spots may also affect the 3D interconnect through-silicon vias (TSVs). For example, difference in the thermal coefficient of TSV material and the silicon on the chip may cause mechanical stress around the TSV region, and may impact the electrical performance of the TSV interconnect.
Current tools cannot model or simulate the thermal gradient of an IC to help designers to design for thermal marginality. For example, existing electronic design automation (EDA) tools cannot model the thermal gradient phenomenon.